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ContactXC95288XL-7PQG208C
0.5mm Tin PMIC XC9500XL Series XC95288XL 208 Pin 3.3V 208-BFQFP
- Manufacturer: Xilinx
- NO: 903-XC95288XL-7PQG208C
- Package: 208-BFQFP
- Datasheet:
- Stock: 2239
- Description: 0.5mm Tin PMIC XC9500XL Series XC95288XL 208 Pin 3.3V 208-BFQFP (Kg)
- Delivery:
- Payment:
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| Parameters | |
|---|---|
| Factory Lead Time | 10 Weeks |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 208-BFQFP |
| Number of Pins | 208 |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 1996 |
| Series | XC9500XL |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| ECCN Code | EAR99 |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 245 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | XC95288XL |
| Pin Count | 208 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Programmable Type | In System Programmable (min 10K program/erase cycles) |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 168 |
| Memory Type | FLASH |
| Propagation Delay | 7.5 ns |
| Turn On Delay Time | 7.5 ns |
| Number of Logic Elements/Cells | 16 |
| Number of Gates | 6400 |
| Max Frequency | 125MHz |
| Speed Grade | 7 |
| Output Function | MACROCELL |
| Number of Macro Cells | 288 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | ROHS3 Compliant |
XC95288XL-7PQG208C Description
The XC95288XL-7PQG208C is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 6 ns. Power dissipation in CPLDs can vary substantially depending on the system frequency, design application, and output loading. To help reduce power dissipation, each macrocell in an XC95288XL-7PQG208C may be configured for low-power mode (from the default high-performance mode).
XC95288XL-7PQG208C Features
6 ns pin-to-pin logic delays
System frequency up to 208 MHz
288 macrocells with 6,400 usable gates
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
XC95288XL-7PQG208C Applications
Automotive
Hybrid, electric & powertrain systems
Enterprise systems
Datacenter & enterprise computing
Personal electronics
Home theater & entertainment
