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STS9D8NH3LL datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from STMicroelectronics stock available at Feilidi
- Manufacturer: STMicroelectronics
- NO: 761-STS9D8NH3LL
- Package: 8-SOIC (0.154, 3.90mm Width)
- Datasheet:
- Stock: 596
- Description: STS9D8NH3LL datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from STMicroelectronics stock available at Feilidi(Kg)
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| Parameters | |
|---|---|
| Peak Reflow Temperature (Cel) | 260 |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | STS9D8 |
| Pin Count | 8 |
| Number of Elements | 2 |
| Operating Mode | ENHANCEMENT MODE |
| Power Dissipation | 2W |
| FET Type | 2 N-Channel (Dual) |
| Transistor Application | SWITCHING |
| Rds On (Max) @ Id, Vgs | 22m Ω @ 4A, 10V |
| Vgs(th) (Max) @ Id | 1V @ 250μA |
| Input Capacitance (Ciss) (Max) @ Vds | 857pF @ 25V |
| Current - Continuous Drain (Id) @ 25°C | 8A 9A |
| Gate Charge (Qg) (Max) @ Vgs | 10nC @ 4.5V |
| Rise Time | 32ns |
| Fall Time (Typ) | 8.5 ns |
| Turn-Off Delay Time | 18 ns |
| Continuous Drain Current (ID) | 9A |
| Gate to Source Voltage (Vgs) | 16V |
| Drain Current-Max (Abs) (ID) | 8A |
| Drain to Source Breakdown Voltage | 30V |
| Avalanche Energy Rating (Eas) | 150 mJ |
| FET Technology | METAL-OXIDE SEMICONDUCTOR |
| FET Feature | Logic Level Gate |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Transistor Element Material | SILICON |
| Operating Temperature | 150°C TJ |
| Packaging | Tape & Reel (TR) |
| Series | STripFET™ |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Resistance | 22MOhm |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FET General Purpose Power |
| Max Power Dissipation | 2W |
| Terminal Form | GULL WING |
STS9D8NH3LL Description
This device uses the latest advanced design rules of ST?ˉs STrip based technology. The Q1 and Q2 transistors, show respectively, the best gate charge and on-resistance for minimizing the switching and conduction losses. This application specific Power MOSFET has been designed to replace two SO-8 packages in DC-DC converters.
STS9D8NH3LL Features
Optimal RDS(on) x Qg trade-off @ 4.5V
?? Conduction losses reduced
?? Switching losses reduced
STS9D8NH3LL Application
?? Switching applications
