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Shipping starts at $40, but some countries will exceed $40. For
example (South Africa, Brazil, India, Pakistan, Israel, etc.)
The basic freight (for package ≤0.5kg or corresponding volume) depends on the time
zone and country.
Currently, our products are shipped through DHL, FedEx, SF, and UPS.
Delivery TimeOnce the goods are shipped, estimated delivery time depends on the shipping methods you chose:
FedEx International, 5-7 business days.
The following are some common countries' logistic time.
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The NUC745 is built around an outstanding CPU core, the 16/32 ARM7TDMI RISC processor which
designed by Advanced RISC Machines, Ltd. It offers 4K-byte I-cache/SRAM and 4K-byte Dcache/SRAM, is a low power, general purpose integrated circuits. Its simple, elegant, and fully static
design is particularly suitable for cost sensitive and power sensitive applications.
One 100/10 Mbit MAC of Ethernet controller is built-in to reduce total system cost.
The NUC745 also provides one USB 1.1 host controller, one USB 1.1 device controller, one AC97/I²S
controller, one 2-channel GDMA, four independent UARTs, one watchdog timer, two 24-bit timers with
8-bit pre-scale, up to 31 programmable I/O ports, PS2 keyboard controller and an advanced interrupt
controller. The external bus interface (EBI) controller provides for SDRAM, ROM/SRAM, flash memory
and I/O devices. The system manager includes an internal 32-bit system bus arbiter and a PLL clock
controller.
With a wide range of serial communication and Ethernet interfaces, the NUC745 is suitable for
communication gateways as well as many other general purpose applications.
FEATURES
Architecture
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
External Bus Interface
• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
• Support for SDRAM
• Programmable access cycle (0-7 wait cycle)
• Four-word depth write buffer for SDRAM write data
• Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
• Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache
• Support for LRU (Least Recently Used) protocol
• Cache can be configured as internal SRAM
• Support cache lock function
Ethernet MAC Controller
• DMA engine with burst mode
• MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
• Data alignment logic
• Endian translation
• 100/10 Mbit per second operation
• Full compliance with IEEE standard 802.3
• RMII interface only
• Station Management Signaling
• On-chip CAM (up to 16 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD generation
