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Delivery TimeOnce the goods are shipped, estimated delivery time depends on the shipping methods you chose:
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The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Weight | 230.4mg |
| Operating Temperature | -55°C~150°C TJ |
| Packaging | Tape & Reel (TR) |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Max Power Dissipation | 1W |
| Current Rating | 4.8A |
| Number of Elements | 2 |
| Power Dissipation | 2.5W |
| FET Type | N and P-Channel |
| Rds On (Max) @ Id, Vgs | 35m Ω @ 4.8A, 10V |
| Vgs(th) (Max) @ Id | 2.8V @ 250μA |
| Input Capacitance (Ciss) (Max) @ Vds | 720pF @ 15V |
| Current - Continuous Drain (Id) @ 25°C | 6.3A 4.8A |
| Gate Charge (Qg) (Max) @ Vgs | 30nC @ 10V |
| Rise Time | 20ns |
| Fall Time (Typ) | 19 ns |
| Turn-Off Delay Time | 40 ns |
| Continuous Drain Current (ID) | 4.8A |
| Gate to Source Voltage (Vgs) | 20V |
| Drain to Source Breakdown Voltage | 30V |
| FET Feature | Logic Level Gate |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
These complementary MOSFET half-bridge devices are produced using Xiantong's proprietary high cell density. DMOS technology. This high-density process is specifically tailored to minimize on-resistance, provide excellent switching performance, and withstand high-energy pulses in avalanche and rectifier modes. When two gates are connected together, these devices are particularly suitable for low-voltage half-bridge applications or CMOS applications.
N-Channel 6.3A30VR=0.035@V=10V P-Channel-4.8A,-30V,R=0.065@Vs=-10V
High density cell design or extremely low Rpsion
High power and current handling capability in a widely used surtace mount package.
Matched pair for equal input capacitance and power capability
low-voltage half-bridge applications
CMOS applications
Please send RFQ , we will respond immediately.