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| Parameters | |
|---|---|
| Mount | Surface Mount |
| Package / Case | SOIC |
| Packaging | Cut Tape (CT) |
| Published | 2007 |
| JESD-609 Code | e0 |
| Number of Terminations | 20 |
| Terminal Finish | Tin/Lead (Sn80Pb20) |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | Clock Drivers |
| Technology | ECL |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Number of Functions | 1 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 20 |
| JESD-30 Code | R-PDSO-G20 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -3.0/-5.5/3.3/5.0V |
| Temperature Grade | INDUSTRIAL |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Circuits | 1 |
| Frequency (Max) | 1GHz |
| Output Characteristics | OPEN-EMITTER |
| Input | PECL |
| Logic IC Type | LOW SKEW CLOCK DRIVER |
| PLL | No |
| Propagation Delay (tpd) | 0.9 ns |
| Number of True Outputs | 4 |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
MC100EP139DWR2 Overview
The Cut Tape (CT) method is used for packaging clock ICs. The SOIC package embeds this Clock PLL. This clock generator ic can sustain a maximum temperature of 240 during reflowing. There are 20 terminations found in this file. This electronic frequency generator requires a voltage of 3.3V. PECL is designed as this clock generator's input. To access the electronic component's full performance, 1 circuits are implemented. RF synthesizers based on this clock provide frequencies up to 1GHz maximum. 5.5V would be the maximum supply voltage for this clock generator. It is safe to use this frequency synthesizer with a supply voltage above 3V. The clock-generating IC is a 20-bit device designed specifically for microprocessors. Featuring an impressive low-temperature operating performance and -40°C functions, this clock generator is sure to impress. Even at 85°C, this frequency synthesizer is possible to last with attenuated performance. Fundamentally, this is a kind of Clock Drivers clock PLL. The frequency generator has a NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V feature to improve the output of clock signals. The clock generator is configured with 4 pins for enabling true outputs. LOW SKEW CLOCK DRIVER logic circuits are primarily constructed using this time clock generator.
MC100EP139DWR2 Features
Available in the SOIC
Supply voltage of 3.3V
4 true outputs
MC100EP139DWR2 Applications
There are a lot of ON Semiconductor MC100EP139DWR2 Clock Generators applications.
- Local oscillators (LOs)
- Walkie-talkies
- Automatic control
- PMR (Professional Mobile Radio)
- Digital logic circuits
- CB radios
- Fiber Channel
- Coherent detection of the signal
- Frequency synthesis
- Cell phones
