FDPC8012S

FDPC8012S datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available at Feilidi


  • Manufacturer: ON Semiconductor
  • NO: 598-FDPC8012S
  • Package: 8-PowerWDFN
  • Datasheet: pdf
  • Stock: 8042
  • Description: FDPC8012S datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available at Feilidi(Kg)

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SPECIFICATIONS

Parameters
FET Type 2 N-Channel (Dual) Asymmetrical
Transistor Application SWITCHING
Rds On (Max) @ Id, Vgs 7m Ω @ 12A, 4.5V
Vgs(th) (Max) @ Id 2.2V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds 1075pF @ 13V
Current - Continuous Drain (Id) @ 25°C 13A 26A
Gate Charge (Qg) (Max) @ Vgs 8nC @ 4.5V
Rise Time 3ns
Fall Time (Typ) 3 ns
Turn-Off Delay Time 34 ns
Continuous Drain Current (ID) 88A
JEDEC-95 Code MO-240BA
Gate to Source Voltage (Vgs) 12V
Drain Current-Max (Abs) (ID) 13A
Drain-source On Resistance-Max 0.007Ohm
Drain to Source Breakdown Voltage 25V
FET Technology METAL-OXIDE SEMICONDUCTOR
FET Feature Logic Level Gate
Height 725μm
Length 3.3mm
Width 3.3mm
Radiation Hardening No
RoHS Status ROHS3 Compliant
Factory Lead Time 12 Weeks
Lifecycle Status ACTIVE (Last Updated: 3 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 8-PowerWDFN
Number of Pins 8
Weight 192mg
Transistor Element Material SILICON
Operating Temperature -55°C~150°C TJ
Packaging Tape & Reel (TR)
Published 2010
Series PowerTrench®
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 8
ECCN Code EAR99
Terminal Finish Tin (Sn)
Subcategory FET General Purpose Power
Max Power Dissipation 2W
Number of Elements 2
Configuration SERIES CONNECTED, CENTER TAP, 2 ELEMENTS WITH BUILT-IN DIODE
Operating Mode ENHANCEMENT MODE
Power - Max 800mW 900mW

FDPC8012S         Description


 The device includes two specialized N-channel MOSFET in the dual package. The switch nodes are connected internally for easy placement and wiring of synchronous step-down converters. The control of MOSFET (Q1) and synchronous FET (Q2) is designed to provide optimal power efficiency.

 

FDPC8012S       Features

 

Q1 N-Channel

Max. RDS(on) = 7.0 m|? at VGS = 4.5 V, ID = 12 A

Q2 N-Channel

Max. RDS(on) = 2.2 m|? at VGS = 4.5 V, ID = 23 A

Low inductance packaging shortens rise/fall times, resulting in lower switching losses

MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing

RoHS Compliant


FDPC8012S        Applications


Server

Computing

Communications

General Purpose Point of Load



In Stock

Please send RFQ , we will respond immediately.