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| Parameters | |
|---|---|
| Factory Lead Time | 13 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-PowerTDFN |
| Number of Pins | 8 |
| Weight | 171mg |
| Transistor Element Material | SILICON |
| Operating Temperature | -55°C~150°C TJ |
| Packaging | Tape & Reel (TR) |
| Published | 2009 |
| Series | PowerTrench® |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin (Sn) |
| Subcategory | FET General Purpose Power |
| Max Power Dissipation | 2.5W |
| Terminal Form | FLAT |
| JESD-30 Code | R-PDSO-F6 |
| Number of Elements | 2 |
| Operating Mode | ENHANCEMENT MODE |
| Case Connection | DRAIN SOURCE |
| Power - Max | 1W |
| FET Type | 2 N-Channel (Dual) Asymmetrical |
| Transistor Application | SWITCHING |
| Rds On (Max) @ Id, Vgs | 10m Ω @ 13A, 10V |
| Vgs(th) (Max) @ Id | 2.7V @ 250μA |
| Input Capacitance (Ciss) (Max) @ Vds | 1605pF @ 15V |
| Current - Continuous Drain (Id) @ 25°C | 13A 18A |
| Gate Charge (Qg) (Max) @ Vgs | 24nC @ 10V |
| Rise Time | 3ns |
| Fall Time (Typ) | 3 ns |
| Turn-Off Delay Time | 24 ns |
| Continuous Drain Current (ID) | 60A |
| Gate to Source Voltage (Vgs) | 20V |
| Drain Current-Max (Abs) (ID) | 13A |
| Drain-source On Resistance-Max | 0.01Ohm |
| Drain to Source Breakdown Voltage | 30V |
| FET Technology | METAL-OXIDE SEMICONDUCTOR |
| FET Feature | Logic Level Gate |
| Feedback Cap-Max (Crss) | 55 pF |
| Height | 1.1mm |
| Length | 5mm |
| Width | 5.9mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
In a twin PQFN packaging, this device has two specialized N-Channel MOSFETs. To make synchronous buck converter placement and routing simple, the switch node has been internally connected. To offer maximum power efficiency, the control MOSFET (Q1) and synchronous SyncFETTM (Q2) have been created.
Maximum rDS(on) at VGS = 10 V, ID = 18 A is 5 m.
Max rDS(on) is 5.2 m at 4.5 V and 17 A.
Shorter rise/fall times due to low inductance packing reduce switching losses.
The best architecture for lower circuit inductance and less switch node ringing is made possible by MOSFET integration.
Conforms to RoHS
Computing
Communications
Point of Load for All Purposes
Laptop VCORE
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