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| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 8-PowerTDFN |
| Number of Pins | 8 |
| Weight | 171mg |
| Transistor Element Material | SILICON |
| Operating Temperature | -55°C~150°C TJ |
| Packaging | Tape & Reel (TR) |
| Published | 2009 |
| Series | PowerTrench® |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| ECCN Code | EAR99 |
| Subcategory | FET General Purpose Power |
| Max Power Dissipation | 2.5W |
| Terminal Form | FLAT |
| Base Part Number | FDMS3660S |
| JESD-30 Code | R-PDSO-F6 |
| Number of Elements | 2 |
| Element Configuration | Dual |
| Operating Mode | ENHANCEMENT MODE |
| Power Dissipation | 2.5W |
| Case Connection | DRAIN SOURCE |
| Turn On Delay Time | 7.7 ns |
| Power - Max | 1W |
| FET Type | 2 N-Channel (Dual) Asymmetrical |
| Transistor Application | SWITCHING |
| Rds On (Max) @ Id, Vgs | 8m Ω @ 13A, 10V |
| Vgs(th) (Max) @ Id | 2.7V @ 250μA |
| Input Capacitance (Ciss) (Max) @ Vds | 1765pF @ 15V |
| Current - Continuous Drain (Id) @ 25°C | 30A 60A |
| Gate Charge (Qg) (Max) @ Vgs | 29nC @ 10V |
| Turn-Off Delay Time | 19 ns |
| Continuous Drain Current (ID) | 30A |
| Threshold Voltage | 1.5V |
| Gate to Source Voltage (Vgs) | 12V |
| Drain Current-Max (Abs) (ID) | 13A |
| Drain to Source Breakdown Voltage | 30V |
| FET Technology | METAL-OXIDE SEMICONDUCTOR |
| FET Feature | Logic Level Gate |
| Nominal Vgs | 1.5 V |
| Feedback Cap-Max (Crss) | 70 pF |
| Height | 1.1mm |
| Length | 5mm |
| Width | 5.9mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 13 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Tin |
| Mount | Surface Mount |
The device includes two dedicated N-channel MOSFET in a dual PQFN package. The switch nodes are connected internally for easy placement and wiring of synchronous step-down converters. Control MOSFET (Q1) and synchronous synchronous FET (Q2) are designed to provide optimal power efficiency.
Q1: N?Channel
? Max rDS(on) = 8 m at VGS = 10 V, ID = 13 A
? Max rDS(on) = 11 m at VGS = 4.5 V, ID = 11 A
Q2: N?Channel
? Max rDS(on) = 1.8 m at VGS = 10 V, ID = 30 A
? Max rDS(on) = 2.2 m at VGS = 4.5 V, ID = 27 A
? Low Inductance Packaging Shortens Rise/Fall Times, Resulting in
Lower Switching Losses
? MOSFET Integration Enables Optimum Layout for Lower Circuit
Inductance and Reduced Switch Node Ringing
? These Devices are Pb?Free and are RoHS Compliant
? Computing
? Communications
? General Purpose Point of Load
? Notebook VCORE
Please send RFQ , we will respond immediately.