FDG6322C

FDG6322C datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available at Feilidi


  • Manufacturer: ON Semiconductor
  • NO: 598-FDG6322C
  • Package: 6-TSSOP, SC-88, SOT-363
  • Datasheet: pdf
  • Stock: 9014
  • Description: FDG6322C datasheet pdf and Transistors - FETs, MOSFETs - Arrays product details from ON Semiconductor stock available at Feilidi(Kg)

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SPECIFICATIONS

Parameters
Polarity/Channel Type N-CHANNEL AND P-CHANNEL
Fall Time (Typ) 8 ns
Turn-Off Delay Time 55 ns
Continuous Drain Current (ID) 220mA
Threshold Voltage 850mV
Gate to Source Voltage (Vgs) 8V
Drain to Source Breakdown Voltage 25V
FET Technology METAL-OXIDE SEMICONDUCTOR
FET Feature Logic Level Gate
Nominal Vgs 850 mV
Height 1mm
Length 2mm
Width 1.25mm
Radiation Hardening No
REACH SVHC No SVHC
RoHS Status ROHS3 Compliant
Lead Free Lead Free
Factory Lead Time 10 Weeks
Lifecycle Status ACTIVE (Last Updated: 2 days ago)
Mount Surface Mount
Mounting Type Surface Mount
Package / Case 6-TSSOP, SC-88, SOT-363
Number of Pins 6
Weight 28mg
Transistor Element Material SILICON
Operating Temperature -55°C~150°C TJ
Packaging Tape & Reel (TR)
Published 2017
JESD-609 Code e3
Pbfree Code yes
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 6
ECCN Code EAR99
Resistance 4Ohm
Terminal Finish Tin (Sn)
Additional Feature LOGIC LEVEL COMPATIBLE
Subcategory Other Transistors
Max Power Dissipation 300mW
Terminal Form GULL WING
Current Rating 220mA
Number of Elements 2
Element Configuration Dual
Operating Mode ENHANCEMENT MODE
Power Dissipation 300mW
FET Type N and P-Channel
Transistor Application SWITCHING
Rds On (Max) @ Id, Vgs 4 Ω @ 220mA, 4.5V
Vgs(th) (Max) @ Id 1.5V @ 250μA
Input Capacitance (Ciss) (Max) @ Vds 9.5pF @ 10V
Current - Continuous Drain (Id) @ 25°C 220mA 410mA
Gate Charge (Qg) (Max) @ Vgs 0.4nC @ 4.5V
Rise Time 8ns

FDG6322C           Description

 

  These dual Numbp channel logic level enhanced mode field effect transistors are produced using proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. The device is designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET. Because there is no need for bias resistors, this dual-digital FET can replace several different digital transistors with different bias resistance values.

 

FDG6322C         Features

 

N-Ch 0.22 A, 25 V,

RDS(ON) = 4.0 |? @ VGS= 4.5 V,

RDS(ON) = 5.0 |? @ VGS= 2.7 V

P-Ch -0.41 A,-25V,

RDS(ON) = 1.1 |? @ VGS= -4.5V,

RDS(ON) = 1.5 |? @ VGS= -2.7V.

Very small package outline SC70-6.

Very low level gate drive requirements allowing direct operation in 3 V circuits (V GS(th) < 1.5 V)

Gate-Source Zener for ESD ruggedness (>6k V Human Body Model).


FDG6322C               Applications

This product is general usage and suitable for many different applications.

 






 


In Stock

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