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| Parameters | |
|---|---|
| Operating Temperature | -55°C~150°C TJ |
| Packaging | Tape & Reel (TR) |
| Published | 1999 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Termination | SMD/SMT |
| ECCN Code | EAR99 |
| Resistance | 1.1Ohm |
| Additional Feature | LOGIC LEVEL COMPATIBLE |
| Subcategory | Other Transistors |
| Voltage - Rated DC | -25V |
| Max Power Dissipation | 300mW |
| Terminal Form | GULL WING |
| Current Rating | -410mA |
| Number of Elements | 2 |
| Element Configuration | Dual |
| Operating Mode | ENHANCEMENT MODE |
| Power Dissipation | 300mW |
| Turn On Delay Time | 7 ns |
| FET Type | 2 P-Channel (Dual) |
| Transistor Application | SWITCHING |
| Rds On (Max) @ Id, Vgs | 1.1 Ω @ 410mA, 4.5V |
| Vgs(th) (Max) @ Id | 1.5V @ 250μA |
| Input Capacitance (Ciss) (Max) @ Vds | 62pF @ 10V |
| Current - Continuous Drain (Id) @ 25°C | 410mA |
| Gate Charge (Qg) (Max) @ Vgs | 1.5nC @ 4.5V |
| Rise Time | 8ns |
| Drain to Source Voltage (Vdss) | 25V |
| Fall Time (Typ) | 8 ns |
| Turn-Off Delay Time | 55 ns |
| Continuous Drain Current (ID) | -410mA |
| Threshold Voltage | -820mV |
| Gate to Source Voltage (Vgs) | -8V |
| Drain Current-Max (Abs) (ID) | 0.41A |
| Drain to Source Breakdown Voltage | -25V |
| Dual Supply Voltage | -25V |
| FET Technology | METAL-OXIDE SEMICONDUCTOR |
| FET Feature | Logic Level Gate |
| Nominal Vgs | -820 mV |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 10 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 2 days ago) |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-TSSOP, SC-88, SOT-363 |
| Number of Pins | 6 |
| Weight | 28mg |
| Transistor Element Material | SILICON |
These dual P-channel logic level enhanced mode field effect transistors are produced using proprietary high cell density DMOS technology. This very high-density process is specially tailored to minimize on-resistance. The device is designed for low-voltage applications as a substitute for bipolar digital transistors and small-signal MOSFET.
N-Ch 0.22 A, 25 V,
RDS(ON) = 4.0 |? @ VGS= 4.5 V,
RDS(ON) = 5.0 |? @ VGS= 2.7 V
P-Ch -0.41 A,-25V,
RDS(ON) = 1.1 |? @ VGS= -4.5V,
RDS(ON) = 1.5 |? @ VGS= -2.7V.
Very small package outline SC70-6.
Very low level gate drive requirements allowing direct operation in 3 V circuits (V GS(th) < 1.5 V)
Gate-Source Zener for ESD ruggedness (>6k V Human Body Model).
This product is general usage and suitable for many different applications.
Please send RFQ , we will respond immediately.