EPM7256AETI144-7

0.5mm PMIC 144 Pin 166.67MHz 3.3V TQFP


  • Manufacturer: Altera
  • NO: 2936-EPM7256AETI144-7
  • Package: TQFP
  • Datasheet: pdf
  • Stock: 3285
  • Description: 0.5mm PMIC 144 Pin 166.67MHz 3.3V TQFP (Kg)

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SPECIFICATIONS

Parameters
JESD-609 Code e0
Pbfree Code no
Part Status Active
Moisture Sensitivity Level (MSL) 3
Number of Terminations 144
ECCN Code 3A991
Terminal Finish Tin/Lead (Sn/Pb)
Max Operating Temperature 85°C
Min Operating Temperature -40°C
Additional Feature YES
HTS Code 8542.39.00.01
Subcategory Programmable Logic Devices
Technology CMOS
Terminal Position QUAD
Terminal Form GULL WING
Peak Reflow Temperature (Cel) 220
Supply Voltage 3.3V
Terminal Pitch 0.5mm
Frequency 166.67MHz
Time@Peak Reflow Temperature-Max (s) 20
Pin Count 144
Operating Supply Voltage 3.3V
Temperature Grade INDUSTRIAL
Max Supply Voltage 3.6V
Min Supply Voltage 3V
Number of I/O 120
Memory Type EEPROM
Propagation Delay 7.5 ns
Turn On Delay Time 7.5 ns
Frequency (Max) 172.4MHz
Programmable Logic Type EE PLD
Number of Gates 5000
Number of Programmable I/O 36
Number of Logic Blocks (LABs) 16
Speed Grade 7
Output Function MACROCELL
Number of Macro Cells 256
JTAG BST YES
In-System Programmable YES
Height Seated (Max) 1.6mm
Length 20mm
Width 20mm
Radiation Hardening No
RoHS Status RoHS Compliant
Lead Free Contains Lead
Factory Lead Time 10 Weeks
Mount Surface Mount
Package / Case TQFP
Number of Pins 144
Published 1998

EPM7256AETI144-7 Overview


There are 256 macro cells. A macro cell is a cell in a mobile phone network that provides radio coverage through the use of a high-power cell site (tower, antenna or mast).There is a TQFP package containing it.As a result, it has 120 I/O ports programmed.The device is programmed with 144 terminations.This electrical part is wired with a terminal position of QUAD.Power is provided by a supply voltage of 3.3V volts.It is a part of the family [0].In this chip, the 144pins are programmed.This device also displays [0].It is possible to construct digital circuits using 5000gates, which are devices that serve as building blocks.High efficiency requires a voltage supply of [0].It is adopted to store data in [0].This device is mounted by Surface Mount.144pins are included in its design.There is a maximum supply voltage of 3.6Vwhen the device is operating.A minimum supply voltage of 3V is required for it to operate.There are 36 programmable I/Os, which are method of data transmissions, via input/output (I/O), between a central processing unit (CPU) and a peripheral device, such as a network adapter or a Parallel ATA storage device. A frequency of 166.67MHzcan be achieved.In order to operate properly, the operating temperature should be higher than -40°C.A temperature less than 85°Cshould be used for operation.There are 16 logic blocks (LABs) in its basic building block.Maximum frequency should be less than 172.4MHz.There are several types of programmable logic that can be categorized as EE PLD.

EPM7256AETI144-7 Features


TQFP package
120 I/Os
144 pin count
144 pins
16 logic blocks (LABs)

EPM7256AETI144-7 Applications


There are a lot of Altera EPM7256AETI144-7 CPLDs applications.

  • Address decoders
  • PLC analog input modules
  • Pattern recognition
  • Random logic replacement
  • ON-CHIP OSCILLATOR CIRCUIT
  • DDC INTERFACE
  • LED Lighting systems
  • Multiple Clock Source Selection
  • Battery operated portable devices
  • STANDARD SERIAL INTERFACE UART

In Stock

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