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The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Package / Case | TQFP |
| Number of Pins | 144 |
| Published | 1998 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 144 |
| ECCN Code | 3A991 |
| Terminal Finish | Matte Tin (Sn) - annealed |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Pin Count | 144 |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 100 |
| Memory Type | EEPROM |
| Propagation Delay | 7.5 ns |
| Turn On Delay Time | 7.5 ns |
| Frequency (Max) | 192.3MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 36 |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 7 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 1.6mm |
| Length | 20mm |
| Width | 20mm |
| Radiation Hardening | No |
| REACH SVHC | Unknown |
| RoHS Status | RoHS Compliant |
EPM7128AETC144-7N Overview
The mobile phone network has 128 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).A TQFP package contains the item.There are 100 I/Os on the board.The termination of a device is set to [0].The terminal position of this electrical component is QUAD.The power source is powered by 3.3Vvolts.It is a part of the family [0].It is programmed with 144 pins.This device can also display [0].There are 2500 gates, which are devices that acts as a building block for digital circuits. In order to achieve high efficiency, the supply voltage should be maintained at [0].It is recommended that data be stored in [0].A Surface Mountis mounted on this electronic component.There are 144 pins embedded in the device.There is a maximum supply voltage of 3.6V.In order for it to operate, a supply voltage of 3Vis required.A programmable I/O count of 36 has been recorded.This can be achieved at a frequency of 125MHz.It is recommended that the operating temperature be higher than 0°C.There should be a temperature below 70°Cat the time of operation.It consists of 8 logic blocks (LABs).It is recommended that the maximal frequency be lower than 192.3MHz.It is possible to classify programmable logic as EE PLD.
EPM7128AETC144-7N Features
TQFP package
100 I/Os
144 pin count
144 pins
8 logic blocks (LABs)
EPM7128AETC144-7N Applications
There are a lot of Altera EPM7128AETC144-7N CPLDs applications.
- Interface bridging
- Protection relays
- Power up sequencing
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- Configurable Addressing of I/O Boards
- STANDARD SERIAL INTERFACE UART
- ROM patching
- Software-driven hardware configuration
- Custom shift registers
- White goods (Washing, Cold, Aircon ,...)
