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ContactEPM7064AETI44-7
0.8mm PMIC 44 Pin 166.67MHz 3.3V TQFP
- Manufacturer: Altera
- NO: 2936-EPM7064AETI44-7
- Package: TQFP
- Datasheet:
- Stock: 7091
- Description: 0.8mm PMIC 44 Pin 166.67MHz 3.3V TQFP (Kg)
- Delivery:
- Payment:
In Stock
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| Parameters | |
|---|---|
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Package / Case | TQFP |
| Number of Pins | 44 |
| Packaging | Bulk |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 44 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 235 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.8mm |
| Frequency | 166.67MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 44 |
| Number of Outputs | 36 |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | INDUSTRIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 36 |
| Memory Type | EEPROM |
| Propagation Delay | 7.5 ns |
| Turn On Delay Time | 7.5 ns |
| Frequency (Max) | 222.2MHz |
| Architecture | PLA-TYPE |
| Programmable Logic Type | EE PLD |
| Number of Gates | 1250 |
| Number of Programmable I/O | 36 |
| Number of Logic Blocks (LABs) | 4 |
| Speed Grade | 7 |
| Output Function | MACROCELL |
| Number of Macro Cells | 64 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height | 950μm |
| Length | 10mm |
| Width | 10mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
EPM7064AETI44-7 Overview
The mobile phone network has 64 macro cells, which are cells that provide radio coverage from high-power cell sites (towers, antennas, or masts).You can find it in package [0].The device has 36inputs and outputs.44terminations have been programmed into the device.This electrical part is wired with a terminal position of QUAD.A voltage of 3.3Vprovides power to the device.The part is included in Programmable Logic Devices.Bulkis the packaging method.There are 44 pins on the chip.It is possible to construct digital circuits using 1250gates, which are devices that serve as building blocks.If high efficiency is desired, the supply voltage should be kept at [0].Data storage is performed using [0].This device is mounted by Surface Mount.There are 44 pins embedded in the device.In this case, the maximum supply voltage is 3.6V.The minimal supply voltage is 3V.A total of 36Programmable I/Os are present.This can be achieved at a frequency of 166.67MHz.The operating temperature should be higher than -40°C.It is recommended that the operating temperature be lower than 85°C.4logic blocks (LABs) make up this circuit.It should be below 222.2MHzat the maximal frequency.There are several types of programmable logic that can be categorized as EE PLD.A 36output is configured for this device.
EPM7064AETI44-7 Features
TQFP package
36 I/Os
44 pin count
44 pins
4 logic blocks (LABs)
36 outputs
EPM7064AETI44-7 Applications
There are a lot of Altera EPM7064AETI44-7 CPLDs applications.
- Boolean function generators
- Pattern recognition
- Interface bridging
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- Power Meter SMPS
- Handheld digital devices
- ToR/Aggregation/Core Switch and Router
- Wide Vin Industrial low power SMPS
- Protection relays
- Multiple Clock Source Selection
