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example (South Africa, Brazil, India, Pakistan, Israel, etc.)
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Delivery TimeOnce the goods are shipped, estimated delivery time depends on the shipping methods you chose:
FedEx International, 5-7 business days.
The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Factory Lead Time | 8 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 256-BGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~85°C TJ |
| Packaging | Tray |
| Series | MAX® II |
| JESD-609 Code | e1 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 256 |
| ECCN Code | 3A991 |
| Terminal Finish | TIN SILVER COPPER |
| Additional Feature | IT CAN ALSO OPERATE AT 3.3V |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 1mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | EPM2210 |
| JESD-30 Code | S-PBGA-B256 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 1.89V |
| Power Supplies | 1.5/3.31.8V |
| Supply Voltage-Min (Vsup) | 1.71V |
| Programmable Type | In System Programmable |
| Number of I/O | 204 |
| Propagation Delay | 11.2 ns |
| Output Function | MACROCELL |
| Number of Macro Cells | 1700 |
| JTAG BST | YES |
| Voltage Supply - Internal | 1.71V~1.89V |
| Delay Time tpd(1) Max | 7ns |
| Number of Logic Elements/Blocks | 2210 |
| Height Seated (Max) | 2.2mm |
| Length | 17mm |
| Width | 17mm |
| RoHS Status | RoHS Compliant |
EPM2210GF256C5N developed by Intel belongs to the family of instant-on, non-volatile CPLDs featuring high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. It is designed based on a 0.18-µm, 6-layer-metal-flash process. Based on its MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), the EPM2210GF256C5N CPLD is able to reduce cost and power, making it well-suited for bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.
MultiVolt core
A user flash memory (UFM) block
Enhanced in-system programmability (ISP)
High I/O counts
Reliable fitting versus other CPLD architectures
Bus bridging
I/O expansion
Power-on reset (POR) and sequencing control
Device configuration control
Please send RFQ , we will respond immediately.