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9FGV0241AKLF datasheet pdf and Clock/Timing - Application Specific product details from Integrated Device Technology (IDT) stock available at Feilidi
- Manufacturer: Integrated Device Technology (IDT)
- NO: 378-9FGV0241AKLF
- Package: QFN
- Datasheet:
- Stock: 3311
- Description: 9FGV0241AKLF datasheet pdf and Clock/Timing - Application Specific product details from Integrated Device Technology (IDT) stock available at Feilidi(Kg)
- Delivery:
- Payment:
In Stock
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| Parameters | |
|---|---|
| Factory Lead Time | 7 Weeks |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Package / Case | QFN |
| Number of Pins | 24 |
| Published | 2006 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 |
| Number of Terminations | 24 |
| ECCN Code | EAR99 |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Subcategory | Clock Generators |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Pin Count | 24 |
| Number of Outputs | 2 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 1.9V |
| Temperature Grade | COMMERCIAL |
| Number of Circuits | 1 |
| Operating Supply Current | 25mA |
| uPs/uCs/Peripheral ICs Type | CLOCK GENERATOR, PROCESSOR SPECIFIC |
| Frequency (Max) | 100MHz |
| Input | Crystal |
| Primary Clock/Crystal Frequency-Nom | 27MHz |
| PLL | Yes |
| Length | 4mm |
| Width | 4mm |
| Thickness | 900μm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
9FGV0241AKLF Description
The 9FGV0241AKLF is a 2-output very low-power frequency generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo=100.
9FGV0241AKLF Features
Integrated terminations provide 100Ω differential Zo; reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and board space
Programmable Slew rate for each output; allows tuning for various line lengths
Programmable output amplitude; allows tuning for various application environments
DIF outputs are blocked until PLL is locked; clean system start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm synthesis error
Configuration can be accomplished with strapping pins; the SMBus interface is not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space-saving 24-pin 4x4 mm VFQFPN; minimal board space
9FGV0241AKLF Applications
Riser Cards
Storage
Networking
JBOD
Communications
Access Points
