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1 Circuit 2GHz 2:8 Clock Buffer IDT8SLVP1208 28-WFQFN Exposed Pad
- Manufacturer: Renesas Electronics America Inc.
- NO: 668-8SLVP1208ANBGI8
- Package: 28-WFQFN Exposed Pad
- Datasheet:
- Stock: 4765
- Description: 1 Circuit 2GHz 2:8 Clock Buffer IDT8SLVP1208 28-WFQFN Exposed Pad(Kg)
- Delivery:
- Payment:
In Stock
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Delivery TimeOnce the goods are shipped, estimated delivery time depends on the shipping methods you chose:
FedEx International, 5-7 business days.
The following are some common countries' logistic time.
| Parameters | |
|---|---|
| Factory Lead Time | 12 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 28-WFQFN Exposed Pad |
| Supplier Device Package | 28-VFQFPN (5x5) |
| Operating Temperature | -40°C~85°C |
| Packaging | Tape & Reel (TR) |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply | 2.375V~3.465V |
| Base Part Number | IDT8SLVP1208 |
| Output | LVPECL |
| Number of Circuits | 1 |
| Frequency (Max) | 2GHz |
| Input | CML, LVDS, LVPECL |
| Ratio - Input:Output | 2:8 |
| Differential - Input:Output | Yes/Yes |
| RoHS Status | ROHS3 Compliant |
8SLVP1208ANBGI8 Overview
There is a case available for the cut smart buffer in 28-WFQFN Exposed Pad. Tape & Reel (TR) is the form in which it is packaged. There is a maximum value of 2GHz for normal operation. In this case, it will be mounted by Surface Mount. This electronic component falls under the classification of Fanout Buffer (Distribution), Multiplexer. It is recommended to set the temperature to -40°C~85°C in order to ensure reliable performance. In general, it should be able to work with a power source of 2.375V~3.465V volts. As a result, the output is LVPECL. Basically, it belongs to the same family as the IDT8SLVP1208.
8SLVP1208ANBGI8 Features
The operating temperature of -40°C~85°C degrees
8SLVP1208ANBGI8 Applications
There are a lot of Renesas Electronics America Inc. 8SLVP1208ANBGI8 Clock Buffers & Drivers applications.
- High speed line receiver
- Aviation
- FPGA
- Fibre channel (FC)
- 5G
- Clock signal level shifting
- Line receiver and signal recovery
- Ultra Mobile PC (UMPC)
- DDR4 JEDEC standard LRDIMM design
- Mass storage system
