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2 Circuit 3.3V Clock Buffer DUAL 20 Pins SSOP
- Manufacturer: Integrated Device Technology (IDT)
- NO: 378-49FCT3805BPYG8
- Package: SSOP
- Datasheet:
- Stock: 8729
- Description: 2 Circuit 3.3V Clock Buffer DUAL 20 Pins SSOP(Kg)
- Delivery:
- Payment:
In Stock
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| Parameters | |
|---|---|
| Moisture Sensitivity Level (MSL) | 1 |
| Number of Terminations | 20 |
| ECCN Code | EAR99 |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Subcategory | Clock Drivers |
| Technology | CMOS |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 2 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 20 |
| Number of Outputs | 10 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Number of Circuits | 2 |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Propagation Delay | 5 ns |
| Quiescent Current | 100nA |
| Family | FCT |
| Output Characteristics | 3-STATE |
| Input | LVTTL |
| Length | 7.2mm |
| Width | 5.3mm |
| Thickness | 1.73mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
| Factory Lead Time | 5 Weeks |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Package / Case | SSOP |
| Number of Pins | 20 |
| Published | 2009 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Active |
49FCT3805BPYG8 Overview
It is package in SSOP case. There are 20 terminations in it. Supply voltages of 3.3V are capable of achieving high efficiency. It is placed in the way of Surface Mount. There are 20 pins on the clock buffer. The 20 pins are used for operation. This clock divider?is econtained in Clock Drivers. At a minimum working temperature of 0°C, it maintains reliable operation. It is possible to achieve stable operation when the maximum operating temperature is set to 70°C. A member of the FCT family, this clock buffer is a digital camera. As a default, it is set to output 10 by default. A maximum supply voltage of 3.6VV can be applied to it. If the source voltage is as low as possible, 3V will work. In order to achieve maximum efficiency, the supply voltage should be kept at 3.3V. The clock divider consumes 100nA quiescent current and is unaffected by external factors.
49FCT3805BPYG8 Features
20 terminations
Clock Drivers subcategory
49FCT3805BPYG8 Applications
There are a lot of Integrated Device Technology (IDT) 49FCT3805BPYG8 Clock Buffers & Drivers applications.
- Clock signal format conversion
- Industrial automation control system
- DDR4 JEDEC standard RDIMM design
- High-end consumer electronics
- Synchronous optical network (SONET)
- OTN
- High reliability telecommunication system
- Machine made
- Clock signal duplication
- Mobile Internet Device (MID)
